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d a t a sh eet product speci?cation october 1999 discrete semiconductors PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor
october 1999 2 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor features symbol quick reference data ? 'trench' technology v dss = 55 v ? very low on-state resistance ? fast switching i d = 75 a ? low thermal resistance r ds(on) 5.8 m w (v gs = 10 v) r ds(on) 6.3 m w (v gs = 5 v) general description siliconmax products use the latest philips trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. applications:- ? d.c. to d.c. converters ? switched mode power supplies the psmn005-55p is supplied in the sot78 (to220ab) conventional leaded package. the PSMN005-55B is supplied in the sot404 surface mounting package. pinning sot78 (to220ab) sot404 (d 2 pak) pin description 1 gate 2 drain 1 3 source tab drain limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v dss drain-source voltage t j = 25 ?c to 175?c - 55 v v dgr drain-gate voltage t j = 25 ?c to 175?c; r gs = 20 k w -55v v gs continuous gate-source - 15 v voltage v gsm peak pulsed gate-source t j 150 ?c - 20 v voltage i d continuous drain current t mb = 25 ?c; v gs = 5 v - 75 2 a t mb = 100 ?c; v gs = 5 v - 75 2 a i dm pulsed drain current t mb = 25 ?c - 240 a p d total power dissipation t mb = 25 ?c - 230 w t j , t stg operating junction and - 55 175 ?c storage temperature d g s 13 tab 2 123 tab 1 it is not possible to make connection to pin:2 of the sot404 package 2 maximum current limited by package
october 1999 3 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor thermal resistances symbol parameter conditions typ. max. unit r th j-mb thermal resistance junction - 0.65 k/w to mounting base r th j-a thermal resistance junction sot78 package, in free air 60 - k/w to ambient sot404 package, pcb mounted, minimum 50 - k/w footprint avalanche energy limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit e as non-repetitive avalanche unclamped inductive load, i as = 75 a; - 268 mj energy t p = 100 m s; t j prior to avalanche = 25?c; v dd 15 v; r gs = 50 w ; v gs = 5 v i as non-repetitive avalanche - 75 a current electrical characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma; 55 - - v voltage t j = -55?c 50 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1.0 1.5 2.0 v t j = 175?c 0.5 - - v t j = -55?c - - 2.3 v r ds(on) drain-source on-state v gs = 10 v; i d = 25 a - 4.8 5.8 m w resistance v gs = 5 v; i d = 25 a - 5.3 6.3 m w v gs = 4.5 v; i d = 25 a - - 6.7 m w v gs = 5 v; i d = 25 a; t j = 175?c - - 13.2 m w i gss gate source leakage current v gs = 10 v; v ds = 0 v - 2 100 na i dss zero gate voltage drain v ds = 55 v; v gs = 0 v; - 0.05 10 m a current t j = 175?c - - 500 m a q g(tot) total gate charge i d = 75 a; v dd = 44 v; v gs = 5 v - 103 - nc q gs gate-source charge - 15 - nc q gd gate-drain (miller) charge - 52 - nc t d on turn-on delay time v dd = 30 v; r d = 1.2 w ; - 45 - ns t r turn-on rise time v gs = 5 v; r g = 10 w - 180 - ns t d off turn-off delay time resistive load - 420 - ns t f turn-off fall time - 235 - ns l d internal drain inductance measured from tab to centre of die - 3.5 - nh l d internal drain inductance measured from drain lead to centre of die - 4.5 - nh (sot78 package only) l s internal source inductance measured from source lead to source - 7.5 - nh bond pad c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 6500 - pf c oss output capacitance - 1500 - pf c rss feedback capacitance - 700 - pf
october 1999 4 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor reverse diode limiting values and characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit i s continuous source current - - 75 a (body diode) i sm pulsed source current (body - - 240 a diode) v sd diode forward voltage i f = 25 a; v gs = 0 v - 0.85 1.2 v i f = 75 a; v gs = 0 v - 1.1 - v t rr reverse recovery time i f = 20 a; -di f /dt = 100 a/ m s; - 80 - ns q rr reverse recovery charge v gs = 0 v; v r = 30 v - 0.2 - m c
october 1999 5 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t mb ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t mb ); conditions: v gs 3 5 v fig.3. safe operating area. t mb = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ) fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ) normalised power derating, pd (%) 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 mounting base temperature, tmb (c) 0.001 0.01 0.1 1 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 1e+00 pulse width, tp (s) transient thermal impedance, zth j-mb (k/w) single pulse d = 0.5 0.2 0.1 0.05 0.02 tp d = tp/t d p t normalised current derating, id (%) 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 mounting base temperature, tmb (c) 0246810 0 100 200 300 400 id/a vds/d vgs\v = 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 6.0 7.0 10.0 1 10 100 1000 1 10 100 drain-source voltage, vds (v) peak pulsed drain current, idm (a) d.c. 100 ms 10 ms rds(on) = vds/ id 1 ms tp = 10 us 100 us 0 20406080100 5 5.5 6 6.5 7 7.5 8 8.5 rds(on)/mohm vgs/v = id/a 3.0 3.2 3.4 3.6 4.0 5.0
october 1999 6 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor fig.7. typical transfer characteristics. i d = f(v gs ) fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ) fig.9. normalised drain-source on-state resistance. r ds(on) /r ds(on)25 ?c = f(t j ) fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz 0 0.5 1 1.5 2 2.5 3 3.5 0 20 40 60 80 100 id/a vgs/v tj = 175 25 threshold voltage, vgs(to) (v) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 junction temperature, tj (c) typical maximum minimum 0 20406080100 0 50 100 150 gfs/s id/a drain current, id (a) 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 0 0.5 1 1.5 2 2.5 3 gate-source voltage, vgs (v) minimum typical maximum normalised on-state resistance 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 junction temperature, tj (c) 100 1000 10000 100000 0.1 1 10 100 drain-source voltage, vds (v) capacitances, ciss, coss, crss (pf) ciss coss crss
october 1999 7 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ) fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. maximum permissible non-repetitive avalanche current (i as ) versus avalanche time (t av ); unclamped inductive load 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 25 50 75 100 125 150 175 200 225 250 gate charge, qg (nc) gate-source voltage, vgs (v) id = 75 a tj = 25 c vdd = 11 v vdd = 44 v 1 10 100 0.001 0.01 0.1 1 10 avalanche time, t av (ms) maximum avalanche current, i as (a) tj prior to avalanche = 150 c 25 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 20 40 60 80 100 if/a vsds/v tj/c = 175 25
october 1999 8 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor mechanical data fig.16. sot78 (to220ab); pin 2 connected to mounting base (net mass:2g) notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to mounting instructions for sot78 (to220ab) package. 3. epoxy meets ul94 v0 at 1/8". references outline version european projection issue date iec jedec eiaj sot78 to-220 d d 1 q p l 123 l 2 (1) b 1 e e b 0 5 10 mm scale plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead to-220 sot78 dimensions (mm are the original dimensions) a e a 1 c note 1. terminals in this zone are not tinned. q l 1 unit a 1 b 1 d 1 e p mm 2.54 qq a b d c l 2 (1) max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.7 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 l 1 e l 97-06-11
october 1999 9 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor mechanical data fig.17. sot404 surface mounting package. centre pin connected to mounting base. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to smd footprint design and soldering guidelines, data handbook sc18. 3. epoxy meets ul94 v0 at 1/8". unit a references outline version european projection issue date iec jedec eiaj mm a 1 d 1 d max. e el p h d q c 2.54 2.60 2.20 15.40 14.80 2.90 2.10 11 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 0 2.5 5 mm scale plastic single-ended surface mounted package (philips version of d 2 -pak); 3 leads (one lead cropped) sot404 e e e b d 1 h d d q l p c a 1 a 13 2 mounting base 98-12-14 99-06-25
october 1999 10 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor mounting instructions dimensions in mm fig.18. sot404 : soldering pattern for surface mounting . definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 17.5 11.5 9.0 5.08 3.8 2.0
october 1999 11 rev 1.200 philips semiconductors product speci?cation PSMN005-55B; psmn005-55p n-channel logic level trenchmos (tm) transistor notes
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